initial commit

This commit is contained in:
Dominic 2024-01-19 12:55:42 +01:00
commit 2ec6d250fe
Signed by: msrd0
GPG key ID: DCC8C247452E98F9
9 changed files with 1038 additions and 0 deletions

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# [target.thumbv7em-none-eabihf]
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*~
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target/

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checksum = "0f3531638e407dfc0814761abb7c00a5b54992b849452a0646b7f65c9f770f3f"
dependencies = [
"proc-macro2",
"quote",
"unicode-ident",
]
[[package]]
name = "unicode-ident"
version = "1.0.12"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0fee4b"
[[package]]
name = "vcell"
version = "0.1.3"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "77439c1b53d2303b20d9459b1ade71a83c716e3f9c34f3228c00e6f185d6c002"
[[package]]
name = "void"
version = "1.0.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d"
[[package]]
name = "volatile-register"
version = "0.2.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "de437e2a6208b014ab52972a27e59b33fa2920d3e00fe05026167a1c509d19cc"
dependencies = [
"vcell",
]

33
Cargo.toml Normal file
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[package]
name = "spidump"
version = "0.0.0"
publish = false
edition = "2021"
[dependencies]
cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
cortex-m-rt = "0.7.3"
panic-halt = "0.2"
[dependencies.embassy-futures]
git = "https://github.com/embassy-rs/embassy"
rev = "3bc6e414f7b1d4b4d138c7e90f7f9e85a7ca2885"
[dependencies.embassy-executor]
git = "https://github.com/embassy-rs/embassy"
rev = "3bc6e414f7b1d4b4d138c7e90f7f9e85a7ca2885"
features = ["arch-cortex-m", "executor-thread"]
[dependencies.embassy-time]
git = "https://github.com/embassy-rs/embassy"
rev = "3bc6e414f7b1d4b4d138c7e90f7f9e85a7ca2885"
features = ["generic-queue"]
[dependencies.embassy-stm32]
git = "https://github.com/embassy-rs/embassy"
rev = "3bc6e414f7b1d4b4d138c7e90f7f9e85a7ca2885"
features = ["exti", "stm32f103c8", "time", "time-driver-tim2", "unstable-pac"]
[dependencies.embassy-sync]
git = "https://github.com/embassy-rs/embassy"
rev = "3bc6e414f7b1d4b4d138c7e90f7f9e85a7ca2885"

32
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//! This build script copies the `memory.x` file from the crate root into
//! a directory where the linker can always find it at build time.
//! For many projects this is optional, as the linker always searches the
//! project root directory -- wherever `Cargo.toml` is. However, if you
//! are using a workspace or have a more complicated build setup, this
//! build script becomes required. Additionally, by requesting that
//! Cargo re-run the build script whenever `memory.x` is changed,
//! updating `memory.x` ensures a rebuild of the application with the
//! new memory settings.
use std::{env, fs::File, io::Write, path::PathBuf};
fn main() {
// Put `memory.x` in our output directory and ensure it's
// on the linker search path.
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
File::create(out.join("memory.x"))
.unwrap()
.write_all(include_bytes!("memory.x"))
.unwrap();
println!("cargo:rustc-link-search={}", out.display());
// By default, Cargo will re-run a build script whenever
// any file in the project changes. By specifying `memory.x`
// here, we ensure the build script is only re-run when
// `memory.x` is changed.
println!("cargo:rerun-if-changed=memory.x");
println!("cargo:rustc-link-arg-bins=--nmagic");
println!("cargo:rustc-link-arg-bins=-Tlink.x");
println!("cargo:rustc-link-arg-bins=-Tdefmt.x");
}

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memory.x Normal file
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/* STM32L476RG */
MEMORY
{
FLASH : ORIGIN = 0x08000000, LENGTH = 1024K
RAM : ORIGIN = 0x20000000, LENGTH = 96K
/* RAM2 : ORIGIN = 0x10000000, LENGTH = 32K */
}

38
rustfmt.toml Normal file
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edition = "2021"
max_width = 90
newline_style = "Unix"
unstable_features = true
# skip generated files
format_generated_files = false
# always use tabs.
hard_tabs = true
tab_spaces = 4
# commas inbetween but not after
match_block_trailing_comma = true
trailing_comma = "Never"
# fix my imports for me
imports_granularity = "Crate"
#group_imports = "One"
# format everything
format_code_in_doc_comments = true
format_macro_matchers = true
# don't keep outdated syntax
use_field_init_shorthand = true
use_try_shorthand = true
# condense Struct { _, _ } to Struct { .. }
condense_wildcard_suffixes = true
# prefer foo(Bar { \n }) over foo(\nBar { \n }\n)
overflow_delimited_expr = true
# I wish there was a way to allow 0..n but not a + 1..b + 2
# However, the later looks so terible that I use spaces everywhere
# https://github.com/rust-lang/rustfmt/issues/3367
spaces_around_ranges = true

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#![no_std]
#![no_main]
#![allow(clippy::unnecessary_literal_unwrap)] // "false positive"
#![warn(rust_2018_idioms)]
#![forbid(elided_lifetimes_in_paths)]
mod spi_slave;
use embassy_executor::Spawner;
use embassy_stm32::{
bind_interrupts,
gpio::{self, Output},
peripherals::USART1,
time::{mhz, Hertz},
usart::{self, Uart},
Config, dma::NoDma
};
use panic_halt as _;
use spi_slave::SpiSlave;
bind_interrupts!(struct Irqs {
USART1 => usart::InterruptHandler<USART1>;
});
fn config() -> Config {
let mut config = Config::default();
config.rcc.hse = Some(mhz(8));
let sysclk = Some(mhz(72));
config.rcc.sys_ck = sysclk;
config.rcc.hclk = sysclk;
config.rcc.pclk1 = Some(Hertz(sysclk.unwrap().0 / 2));
config.rcc.pclk2 = sysclk;
config
}
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let p = embassy_stm32::init(config());
let uart1_cfg = usart::Config::default();
let mut uart1 = Uart::new(
p.USART1, p.PA10, p.PA9, Irqs, p.DMA1_CH4, NoDma, uart1_cfg
)
.unwrap();
let spi1_cfg = spi_slave::Config::default();
let mut spi1 = SpiSlave::new(
p.SPI1, p.PA5, p.PA7, p.PA6, p.PA4, p.DMA1_CH3, p.DMA1_CH2, spi1_cfg
);
let _led = Output::new(p.PC13, gpio::Level::Low, gpio::Speed::Low);
let mut buf = [0u8; 4];
loop {
spi1.read(&mut buf).await.unwrap();
uart1.write(&buf).await.unwrap();
}
}

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src/spi_slave.rs Normal file
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use embassy_futures::join::join;
use embassy_stm32::{
dma::Transfer,
gpio::{self, low_level::AFType, AnyPin},
into_ref,
pac::spi::vals,
spi::{
self, BitOrder, CsPin, Error, Instance, MisoPin, Mode, MosiPin, Phase, Polarity,
RxDma, SckPin, TxDma
},
Peripheral, PeripheralRef
};
/// SPI configuration.
#[non_exhaustive]
#[derive(Copy, Clone)]
pub struct Config {
/// SPI mode.
pub mode: Mode,
/// Bit order.
pub bit_order: BitOrder
}
impl Default for Config {
fn default() -> Self {
Self {
mode: spi::Config::default().mode,
bit_order: BitOrder::MsbFirst
}
}
}
impl Config {
fn raw_phase(&self) -> vals::Cpha {
match self.mode.phase {
Phase::CaptureOnSecondTransition => vals::Cpha::SECONDEDGE,
Phase::CaptureOnFirstTransition => vals::Cpha::FIRSTEDGE
}
}
fn raw_polarity(&self) -> vals::Cpol {
match self.mode.polarity {
Polarity::IdleHigh => vals::Cpol::IDLEHIGH,
Polarity::IdleLow => vals::Cpol::IDLELOW
}
}
fn raw_byte_order(&self) -> vals::Lsbfirst {
match self.bit_order {
BitOrder::LsbFirst => vals::Lsbfirst::LSBFIRST,
BitOrder::MsbFirst => vals::Lsbfirst::MSBFIRST
}
}
}
pub struct SpiSlave<'d, T: Instance, Tx, Rx> {
_peri: PeripheralRef<'d, T>,
sck: Option<PeripheralRef<'d, AnyPin>>,
mosi: Option<PeripheralRef<'d, AnyPin>>,
miso: Option<PeripheralRef<'d, AnyPin>>,
cs: Option<PeripheralRef<'d, AnyPin>>,
txdma: PeripheralRef<'d, Tx>,
rxdma: PeripheralRef<'d, Rx>
}
impl<'d, T: Instance, Tx, Rx> SpiSlave<'d, T, Tx, Rx> {
/// Create a new SPI driver.
pub fn new(
peri: impl Peripheral<P = T> + 'd,
sck: impl Peripheral<P = impl SckPin<T>> + 'd,
mosi: impl Peripheral<P = impl MosiPin<T>> + 'd,
miso: impl Peripheral<P = impl MisoPin<T>> + 'd,
cs: impl Peripheral<P = impl CsPin<T>> + 'd,
txdma: impl Peripheral<P = Tx> + 'd,
rxdma: impl Peripheral<P = Rx> + 'd,
config: Config
) -> Self {
into_ref!(peri, sck, mosi, miso, cs);
sck.set_as_af(sck.af_num(), AFType::Input);
sck.set_speed(gpio::Speed::VeryHigh);
mosi.set_as_af(mosi.af_num(), AFType::OutputPushPull);
mosi.set_speed(gpio::Speed::VeryHigh);
miso.set_as_af(miso.af_num(), AFType::Input);
miso.set_speed(gpio::Speed::VeryHigh);
cs.set_as_af(cs.af_num(), AFType::Input);
cs.set_speed(gpio::Speed::VeryHigh);
Self::new_inner(
peri,
Some(sck.map_into()),
Some(mosi.map_into()),
Some(miso.map_into()),
Some(cs.map_into()),
txdma,
rxdma,
config
)
}
fn new_inner(
peri: impl Peripheral<P = T> + 'd,
sck: Option<PeripheralRef<'d, AnyPin>>,
mosi: Option<PeripheralRef<'d, AnyPin>>,
miso: Option<PeripheralRef<'d, AnyPin>>,
cs: Option<PeripheralRef<'d, AnyPin>>,
txdma: impl Peripheral<P = Tx> + 'd,
rxdma: impl Peripheral<P = Rx> + 'd,
config: Config
) -> Self {
into_ref!(peri, txdma, rxdma);
let cpha = config.raw_phase();
let cpol = config.raw_polarity();
let lsbfirst = config.raw_byte_order();
T::enable_and_reset();
T::REGS.cr2().modify(|w| {
w.set_ssoe(false);
});
T::REGS.cr1().modify(|w| {
w.set_cpha(cpha);
w.set_cpol(cpol);
w.set_mstr(vals::Mstr::SLAVE);
w.set_spe(true);
w.set_lsbfirst(lsbfirst);
w.set_ssm(false);
w.set_crcen(false);
w.set_bidimode(vals::Bidimode::UNIDIRECTIONAL);
if mosi.is_none() {
w.set_rxonly(vals::Rxonly::OUTPUTDISABLED);
}
w.set_dff(vals::Dff::EIGHTBIT);
});
Self {
_peri: peri,
sck,
mosi,
miso,
cs,
txdma,
rxdma
}
}
/// SPI read, using DMA.
pub async fn read(&mut self, data: &mut [u8]) -> Result<(), Error>
where
Tx: TxDma<T>,
Rx: RxDma<T>
{
if data.is_empty() {
return Ok(());
}
T::REGS.cr1().modify(|w| {
w.set_spe(false);
});
// clear rxfifo
while T::REGS.sr().read().rxne() {
let _ = T::REGS.dr().read();
}
T::REGS.cr2().modify(|w| w.set_rxdmaen(true));
let clock_byte_count = data.len();
let rx_request = self.rxdma.request();
let rx_src = T::REGS.dr().as_ptr() as *mut u8;
let rx_f = unsafe {
Transfer::new_read(
&mut self.rxdma,
rx_request,
rx_src,
data,
Default::default()
)
};
let tx_request = self.txdma.request();
let tx_dst = T::REGS.dr().as_ptr() as *mut u8;
let clock_byte = 0x00u8;
let tx_f = unsafe {
Transfer::new_write_repeated(
&mut self.txdma,
tx_request,
&clock_byte,
clock_byte_count,
tx_dst,
Default::default()
)
};
T::REGS.cr2().modify(|w| w.set_txdmaen(true));
T::REGS.cr1().modify(|w| {
w.set_spe(true);
});
#[cfg(any(spi_v3, spi_v4, spi_v5))]
T::REGS.cr1().modify(|w| {
w.set_cstart(true);
});
join(tx_f, rx_f).await;
// finish dma
while T::REGS.sr().read().bsy() {}
T::REGS.cr1().modify(|w| {
w.set_spe(false);
});
T::REGS.cr2().modify(|reg| {
reg.set_txdmaen(false);
reg.set_rxdmaen(false);
});
Ok(())
}
}